System and method for providing an arbitrated memory bus in a hybrid computing system

ABSTRACT

A computing system having at least one microprocessor and a memory subsystem coupled to the at least one microprocessor. A memory controller is coupled to manage memory transactions between the memory subsystem and the at least one microprocessor. At least one arbitration port is coupled to the memory controller and configured to receive an external arbitration signal.

CROSS REFERENCE TO RELATED PATENT APPLICATIONS

The present invention is a continuation of U.S. patent application Ser.No. 10/284,994 filed Oct. 31, 2002 for: “System and Method For ProvidingAn Arbitrated Memory Bus In A Hybrid Computing System”, U.S. patentapplication Ser. No. 09/755,744 filed Jan. 5, 2001 for: “MultiprocessorComputer Architecture Incorporating a Plurality of Memory AlgorithmProcessors in the Memory Subsystem” which is a divisional application ofU.S. patent application Ser. No. 09/481,902 filed Jan. 12, 2000 (nowU.S. Pat. No. 6,247,110) which is a continuation application of U.S.patent application Ser. No. 08/992,763 filed Dec. 17, 1997 (now U.S.Patent No. 6,076,152). The present invention is also related to thesubject matter of U.S. Pat. No. 6,339,819 issued Jan. 15, 1992 for:“Multiprocessor with Each Processor Element Accessing Operands in LoadedInput Buffer and Forwarding Results to FIFO Output Buffer”. Theforegoing patent application and issued patents are assigned to SRCComputers, Inc., assignee of the present invention, the disclosures ofwhich are herein specifically incorporated in their entirety by thisreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention.

The present invention relates, in general, to the field of computersystems and techniques for interconnecting various processing orcomputing elements. More particularly, the present invention relates toa computer system architecture and memory controller having anarbitration interface enabling external devices to access system memoryresources cooperatively.

2. Relevant Background.

Conventional computer system architecture for single-processor systemsinclude a microprocessor that communicates with other devices through a“system chipset”. The system chipset implements various input/output andcontroller functions that enable the microprocessor to communicate withexternal devices such as memory, mass storage, display devices, networkinterfaces, printers, and the like. A typical system chipset willimplement an interface to the microprocessor often referred to as a“front side bus” or “FSB” that couples to high-speed, low-latency, orbandwidth intensive components such as memory. The chipset implements asecondary interface, often referred to as a “peripheral bus” thatoperates at a lower speed couples to lower speed devices such as massstorage controllers, printers, network interfaces, and the like.

The system chipset is often produced as multiple specialized components.In a typical configuration, a “north bridge” component implements themicroprocessor interface and an interface to the memory subsystem. A“south bridge” component implements the peripheral interface. The northbridge and south bridge components are coupled to bridge the peripheralinterface with the microprocessor interface. The interface between themicroprocessor and memory is a particularly constrained interface formost applications. In most personal computer architectures, it isassumed that one device will have exclusive access to the FSB (e.g., thesingle microprocessor being coupled to the FSB). Because of this, allmemory transactions must be implemented through a port to the northbridge chip. This increases the system memory access time for theexternal devices. In the case of hybrid computing systems in which theexternal device is an adaptive processor, this increase in access timereduces the performance benefits of the hybrid system.

In many cases, a direct memory access (DMA) controller is implemented onthe peripheral bus, within the north bridge device, or through a DMAport on the north bridge component to manage memory transactions betweenthe peripheral bus and the memory subsystem. DMA controllers aretypically designed to support memory transactions with lower speedperipherals coupled through the south bridge device, as opposed todevices that require significant memory bandwidth such as externalprocessors. In other words, the DMA controller supports peripheralmemory activity, and so operates at the slower peripheral interfacespeeds. While DMA controllers relieve the microprocessor from handlingall memory operations, the slower speed interface limits the ability toaccess the memory subsystem at speeds similar to those available to themicroprocessor.

The north bridge of a traditional computer system internally arbitratesbetween the processor, the graphics port, and peripheral devices and DMAcontroller for access to the system memory bus. Currently, systemchipsets do not provide external access to the arbitration logic. Hence,external devices that desire to access the memory subsystem areconstrained to use the arbitration mechanisms implemented by the northbridge component.

SMP (symmetric multiprocessing) refers to systems that execute programsusing multiple processors that share a common operating system andmemory. In symmetric multiprocessing, the processors share memory andthe I/O bus or data path. A single copy of the operating system is incharge of all the processors. Because conventional computing systemarchitectures do not enable multiple devices to access the memory bus,implementing systems in which multiple processors share memory isdifficult. As a result, SMP systems based on mass-produced componentsthat are designed for conventional architectures have used lower-speedaccess granted at peripheral bus speeds, or implemented processingcomponents within the memory subsystem. An example of the laterimplementation is the multi-adaptive processor (MAP™) described incommonly assigned U.S. Pat. No. 6,247,110 (MAP is a trademark orregistered trademark of SRC Computers, Inc.).

In view of the above, it is apparent that a need exists for a computingsystem that exposes the arbitration mechanisms to enable access to amemory subsystem at high speed. Moreover, there is a particular need forsystem chipset architectures that utilize an externally providedarbitration signal such that a memory subsystem bus can be accessed bymultiple agents such as multiple processors and other components thatcouple to the memory subsystem bus.

SUMMARY OF THE INVENTION

Briefly stated, the present invention involves a computing system havingat least one microprocessor and a memory subsystem coupled to the atleast one microprocessor. A memory controller is coupled to managememory transactions between the memory subsystem and the at least onemicroprocessor. At least one arbitration port is coupled to the memorycontroller and configured to receive an external arbitration signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a functional block diagram of a typical computing systemimplemented with a microprocessor, memory and a system chipset includinga (“North Bridge”) and a peripheral bus controller (“South Bridge”);

FIG. 2 illustrates a functional block diagram of a memory-connectedhybrid computing system including a microprocessor and an adaptiveprocessor coupled to system memory in accordance with the presentinvention;

FIG. 3 is a functional block diagram of an alternative embodiment hybridcomputing system in accordance with the present invention having one ormore adaptive processors coupled to shared system memory with amicroprocessor;

FIG. 4 shows a functional block diagram of a hybrid symmetricalmultiprocessing (SMP) computing system in accordance with the presentinvention in which a memory system arbiter mechanism and port isimplemented in the north bridge component of the system chipset;

FIG. 5 illustrates a functional block diagram of an alternativeconfiguration hybrid SMP computing system having multiple adaptiveprocessors coupled to an arbitrated-access shared memory subsystem inaccordance with the present invention;

FIG. 6 shows a functional block diagram of an alternative embodimenthybrid SMP computing system having memory system access arbitrationmechanisms implemented in a switch/network adapter port (SNAP)implemented in a in accordance with the present invention;

FIG. 7 is a functional block diagram of another alternative embodimenthybrid SMP computing system having multiple adaptive processors withmemory system access arbitration mechanisms implemented in aswitch/network adapter port (SNAP) implemented in a in accordance withthe present invention;

FIG. 8 shows a timing diagram of a first embodiment arbitration sequenceuseful in a two-wire implementation of an arbitration signal bus/port inaccordance with the present invention; and

FIG. 9 shows a timing diagram of a first embodiment arbitration sequenceuseful in a three-wire implementation of an arbitration signal bus/portin accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention involves multiprocessor and hybrid computersystems, including symmetric multiprocessing (SMP) computing systemsthat enable shared access to system memory from the various processes.In exemplary implementations of the present invention, substantiallyconventional system chipsets are modified to expose internal arbitrationlogic to external devices. In this manner, one or more external devices,such as adaptive processors, have a direct link to the system memorywithout need to access system memory through the system chipset. Inother implementations, arbitration logic is implemented in devicesexternal to the system chipset, in which case the system chipset ismodified to arbitrate for memory system access rather than assume it hasexclusive access. In either case, modifications to the system chipsetare minimal, and an arbitration signal bus or port may be implementedwith as few as two or three connections to the system chipset.

FIG. 1 shows a high-level functional block diagram of a typicalcomputing system 100 is shown. The computing system 100 may be, forexample, a personal computer (“PC”) architecture that incorporates acommercially available integrated circuit (“IC”) memory controller(“north bridge”) 102 such as the P4X333/P4X400 devices available fromVIA Technologies, Inc.; the M1647 device available from Acer Labs, Inc.and the 824430X device available from Intel Corporation. North bridge102 is coupled by means of a front side bus (“FSB”) to a processor 104such as one of the Intel® Pentium® series or Xeon™ series of processorsalso available from Intel Corporation. North bridge 102 is coupled via amemory bus to system memory 106, which comprises, for example, anarrangement of synchronous dynamic random access (“SDRAM”) memorymodules. Other memory configurations and devices such as double datarate (DDR) SDRAM, RDRAM and DRDRAM by Rambus Corporation, Enhanced SDRAM(ESDRAM) produced by Ramtron International Corporation, and the like. Asnoted hereinbefore, conventional north bridge components are configuredto support a single processor 104 over the FSB, which makes addingadditional processors difficult. Even where the system chipset supportmultiple processors coupled to the FSB, as described in alternativeembodiments, the FSB architecture is very specific to a particularprocessor type. Hence, coupling advanced or special-purpose processingdevices such as an adaptive processor in a manner that gives theadaptive processor suitable access to the memory subsystem 106 has beendifficult or impossible.

In some implementations, a dedicated accelerated graphics port (“AGP”),not shown, is provided for interfacing system 100 to external graphicsprocessing components while an inter-bridge bus couples north bridge IC102 to a “south bridge” 108. The north bridge 102 and south bridge 108are together referred to as a system chipset as they are typicallydesigned to work together to provide desired system I/O functionality.The allocation of functionality between the components of a chipset maybe altered between implementations, and some or all of the I/Ofunctionality may be integrated into a microprocessor 104 as in the caseof a microcontroller. For purposes of the present invention, it issufficient to note that the north bridge component 102 handles thehigh-speed I/O functions typically associated with accessing a memorysubsystem.

South bridge 108 may be implemented by, for example, an SLC90E66 deviceavailable from Standard Microsystems, Corporation or the VT8235 deviceavailable from VIA Technologies. South bridge 108 implements a varietyof I/O interfaces and ports that couple system 100 to, for example, aperipheral component interconnect (“PCI”) bus, universal serial bus(USB), IEEE 1394 port, system management (“SM”) bus, general purpose(“GP”) I/O as well as industry standard architecture/extended I/O(“ISA/EIO”) bus and the like. South bridge 108 may also implementspecial purpose ports to graphics devices, audio devices, local areanetwork devices, disk drives, flash memory, and the like depending onthe needs of a particular application. In general, the interfaces ofsouth bridge 108 handle slower, narrow bandwidth I/O as compared tonorth bridge 102.

In contrast with the architecture shown in FIG. 1, the hybrid computingsystems shown in FIG. 2-FIG. 7 illustrate various implementation thatenable a external processing devices to share access to a memorysubsystem. Hybrid computer systems are those that incorporate bothstandard microprocessors and adaptive processors. These are typicallylarge multiprocessor server-type systems that reside on a sharednetwork. The overall performance and flexibility of such systems isdirectly proportional to the level of coupling between themicroprocessors and the adaptive processors and system memory. When thedisparate processor types are treated as peers and have balanced (e.g.,substantially equal) bandwidths and latencies to a shared memory, thesystem performance will usually be maximized. In general, theimplementations shown in FIG. 2-FIG. 7 provide an arbitration port andarbitration mechanism that enables an external processor tocooperatively share access to a memory subsystem to achieve suchbalanced access.

For example, in FIG. 2, system 200 expands on the typical computersystem 100 by adding an adaptive processor 210 coupled to the systemmemory bus through a system/network adapter port (SNAP) 212. An adaptiveprocessor such as a multi-adaptive processor (MAP) introduced by SRCComputers, Inc, provide users the capability of having hardwarelogic-implemented functions, which can greatly accelerate applicationalgorithms over what is otherwise implemented in software within aconventional microprocessor 204. Details of an exemplary SNAPimplementation and functionality are described in U.S. patentapplication Ser. No. 09/932,330 filed Aug. 17, 2001 for: “Switch/NetworkAdapter Port for Clustered Computers Employing a Chain of Multi-AdaptiveProcessors in a Dual In-Line Memory Module Format” assigned to SRCComputers, Inc., Colorado Springs, Colo., assignee of the presentinvention, the disclosure of which is herein specifically incorporatedin its entirety by this reference. SNAP 212 is typically placed in aDIMM slot of a computer system, and is thereby coupled to the memorybus. While SNAP 202 is implemented on the memory subsystem and occupiesmemory address space, it is a configurable device that can be configuredto perform processing and I/O functions. Although a SNAP 212 is closelycoupled to the memory system 206, it exhibits some overhead inconducting memory transactions as a result of its “slave” with respectto the memory bus. However, this overhead minimally impacts overallperformance because as the overhead incurred when setting up thearbitration signal port is spread out over all the memory transactionsthat are processed by adaptive processor 210.

In hybrid system 200, memory and I/O controller 202, implemented as anorth bridge chip in the example, can no longer assume thatmicroprocessor 204 will be the only agent that will have control ofsystem memory 206. Adaptive processor 210 requires shared access tosystem memory 206 to begin memory transactions (i.e., read, write,modify, lock, unlock, and the like). In accordance with thisimplementation of the present invention, arbitration logic within memoryand I/O controller 202 is provided with an external arbitration port tocommunicate arbitration signals between SNAP 212 and memory and I/Ocontroller 202. The arbitration signals comprise, in a particularexample, a relatively simple request/grant scheme in which a requestsignal is asserted by an agent that seeks memory system access, and agrant signal is asserted by the arbitration logic to the agent thatcurrently has access to the memory subsystem. As the arbitration logicwithin a conventional north bridge chip already includes logic for suchdecision making, it is a relatively straightforward effort to provide aport (e.g., I/O pins, driver mechanisms, and perhaps buffers) forexternal arbitration signals called for by the present invention.

In operation, for an adaptive processor to become an arbitrating agenton the system memory bus of hybrid system, some motherboard layoutchanges would be needed. A Switch Network Adapter Port (SNAP) would beplaced in one of the DIMM slots in the system. An additional header isadded to the motherboard to provide connections to the chip selects ofthe other DIMM modules in the system. SNAP connects into this header areprovided though a ribbon cable. This header would be 18 to 20 pins insize, for example. In a conventional computer system 100, this header isunused and not populated on the motherboard. From this slot, SNAP 212drives the address and command information to the other DIMM's in thesystem. Data is transferred to and from SNAP 212 across the data linescommon to all DIMMs. The standard SSTL2 interface used in SDRAM's allowsfor multiple drivers to be present on the bus, thus the presentinvention may be implemented without requiring additional tri-statecapability. As a result, the present invention contemplates minormodifications of the system chipset and motherboard and no modificationsof conventional DIMM memory components.

In particular implementations of the present invention, the north bridge202 is designed to be compatible with conventional systems such a system100 in FIG. 1. Such compatibility enables the manufacture of a single ICthat meets the demands of both conventional system 100 and hybrid system200, typically resulting in more efficient manufacturing. In such animplementation, the request line can be tied to an inactive state forconventional systems 100, which would make the memory and I/O controllerthe sole agent arbitrating for memory system access.

With an ability to access memory subsystem 206 directly, the additionalagents such as adaptive processor 210 see a low latency, and higherbandwidth memory accesses. In addition, microprocessor 204 is not neededin the data movement to adaptive processor 210, thus freeingmicroprocessor 204 to perform other non-memory related tasks.

FIG. 3 illustrates another embodiment of a hybrid system 300 in whichthe present invention is implemented. In the embodiment of FIG. 3,multiple adaptive processors 310 are provided using a crossbar 314 tocouple to SNAP 312. Although not shown, more than one SNAP 312 andmicroprocessor system can be connected into the crossbar switch 314.Adaptive processors 310 are substantially equivalent to processor 210 inthe description of FIG. 2, and SNAP device 312 is substantiallyequivalent to SNAP 212 in FIG. 2. In the implementation of FIG. 3,crossbar 314 selectively couples one adaptive processor 310 to SNAP 312such that from the perspective of SNAP 312, a single adaptive processor310 is connected. In this manner, SNAP 312 can be programmed to coupleadaptive processors 310 to the memory bus and memory subsystem 306 is amanner substantially equivalent to that described in the implementationof FIG. 2. Crossbar 314 will require some form of arbitration/control toselect a specific processor 310 to couple to SNAP 312. In a particularexample, this control function is implemented in the SNAP 312 interfaceand leverages control functions defined for communication with adaptiveprocessors 310, hence, no additional wiring or resources are required toimplemented control of crossbar 314. This can be implemented, forexample, by logic configured within one or more of adaptive processors310, or by an external management agent (not shown). Alternatively,crossbar 314 may implement a round-robin selection of adaptiveprocessors 310 to implement a time-sharing like algorithm for access tosystem memory 306.

FIG. 4 illustrates a hybrid system that differs from that shown in FIG.2 in that a plurality of processors 404 are coupled to the FSB incombination with external access to the memory bus. Adaptive processors410 are substantially equivalent to processor 210 in the description ofFIG. 2, and SNAP device 412 is substantially equivalent to SNAP 212 inFIG. 2. Some system chipsets include a memory and I/O controller 402that can interface with multiple microprocessors 402 on the FSB. Thememory transactions generated by microprocessors 404 are arbitrated withtransaction requests from adaptive processor 410 to enable shared accessto system memory 406. Memory and I/O controller 402 may implement equalaccess to all processors 404 and 410, or may offer preferred access tosome. For example, all of the microprocessors 404 together may bet 50%access, while the remaining 50% is allocated to adaptive processor 410.Enabling variable access bandwidth may require some modifications to thearbitration logic within memory and I/O controller 402. It iscontemplated that the programming within SNAP 412 may also be modifiedto account for more demanding access by processors 404, for example, byregulating or governing the frequency with which adaptive processor 410is allowed to access system memory 406.

FIG. 5 illustrates an implementation in which multiple processors 504share FSB access to memory and I/O controller 502 while multipleadaptive processors 510 access memory and I/O controller 502 throughSNAPs 512. Because SNAP devices 512 are configurable, they can beconfigured to operate in parallel. SNAP-to-SNAP connection 512 may be aphysical connection, or a virtual connection implemented through memorycommands. Each adaptive processor 510 has access to the memory bus andtherefore arbitrated access to system memory 506. The implementation ofFIG. 5 leverages the arbitration mechanisms within memory and I/Ocontroller 502 which include the ability to arbitrate amongst multiplerequesting agents. SNAPs 512 include mechanisms to coordinate memory busaccess amongst themselves, and may include mechanisms to self-govern thefrequency with which memory bus accesses are asserted to account forincreased access by multiple microprocessors 504.

FIG. 6 and FIG. 7 illustrate exemplary embodiments in which arbitrationcontrol logic is implemented within a SNAP 612 or SNAP 712 rather thanrelying entirely on arbitration logic within a memory and I/O controller602 or 702. In some cases, the manufacturer of memory and I/O controller602/702 may provide external access to the memory bus without directaccess to the arbitration mechanisms. In this case, arbitration logicwithin SNAPs 612 and 712 will monitor the memory refresh signal on thememory bus. In a particular implementation, the memory refresh controlis retained in the north bridge component 602/702 so that it remainscompatible with conventional computer systems.

FIG. 6 is a SMP computer system 600 that is similar to that shown inFIG. 4, but differs in that SNAP 612 implements arbitration logicexternal to memory and I/O controller 602. This external arbitrationlogic enables adaptive processor 610 to access memory subsystem 606. Thememory and I/O component 602 asserts a request signal when an access tosystem memory is pending from one of microprocessors 604 or I/O bridge608. Memory refresh is implemented by causing memory and I/O component602 to assert a refresh signal to SNAP 612 before a refresh cycle. Onthe next command cycle following the refresh signal, the memory refreshmechanisms within memory and I/O component 606 controls the memory busto perform refresh of system memory 606.

FIG. 7 shows a SMP computer system 700 that is similar to that shown inFIG. 5, but differs in that SNAP 712 implements arbitration logicexternal to memory and I/O controller 702. Like the implementation ofFIG. 6, the use of external arbitration logic is implemented byproviding a refresh signal from memory and I/O controller 702 to atleast one SNAP 712 so that refresh functionality is retained by memoryand I/O controller 702. To use memory and I/O controller 702 in aconventional computer system 100, the grant line is tied to a signallevel indicating that the memory and I/O controller 702 is in control ofthe memory bus.

FIG. 8 and FIG. 9 illustrate exemplary timing diagrams for operating acomputer system in accordance with the present invention. In FIG. 8 andFIG. 9, the horizontal access represents increasing time, divided intocycles indicated by the clock signal. The vertical access representssignal level (e.g., voltage, current, or the like) indicating signalevents over time. The request and grant signals in FIG. 8 indicate thestate of the arbitration bus labeled “ARB” in FIG. 2-FIG. 5. The requestand grant signals in FIG. 8 indicate the state of the arbitration buslabeled “ARB” in FIG. 6 and FIG. 7, while the refresh signal line inFIG. 9 indicates the state of the refresh line shown in FIG. 6 and FIG.7. In the upper region of each timing diagram clock cycles aredesignated “NB CMD” to indicate a time period when a north bridgecommand is asserted. (i.e. a command asserted by memory and I/Ocontroller). In cycles labeled “SNAP CMD”, a SNAP device controls thearbitrated memory bus, and in cycles labeled “REFRESH CMD” in FIG. 9,the refresh mechanisms (in the north bridge component in the particularexamples) control the arbitrated memory bus. For convenience, thediscussion of FIG. 8 and FIG. 9 will refer to a SNAP signal as a signalgenerated by any of SNAP devices 212, 312, 412, 512, 612, or 712.Likewise, memory and I/O controllers 202, 302, 402, 30 502, 602, and 702will be referred to as the north bridge component.

In FIG. 8, the north bridge is initially in control of the memory bus. ASNAP device asserts a REQUEST signal, which is held in a request stateuntil a GRANT is received one or more clock cycles later. The GRANT willbe generated by the arbitration logic within the north bridge componentaccording to arbitration algorithms implemented by the particular northbridge component. Upon assertion of a GRANT signal, the SNAP device hascontrol of the memory bus until it releases the memory bus by droppingthe REQUEST line. It is contemplated that some mechanism may be providedto force the SNAP device to relinquish control of the memory bus toavoid deadlock/live-lock situations. However, in the normal operationshown in FIG. 8, the arbitration logic within the north bridge componentrecognizes the de-assertion of the REQUEST signal and places the GRANTline low in a subsequent clock cycle, after which, the north bridgecomponent retains control of the memory bus until a subsequent SNAPrequest is handled. For conventional operation, the GRANT line is tiedpermanently to a signal state indicating north bridge control (e.g., lowin FIG. 8) so that north bridge component retains continuous control.

In FIG. 9, the north bridge is initially in control of the memory bus.The REQUEST/GRANT protocol is largely similar to that shown in FIG. 8,however, because arbitration logic is implemented in the SNAP devices,the SNAP device must be made aware of the REFRESH state of the memorysystem. As shown in FIG. 9, upon detection of a REFRESH signalindicating that the north bridge component is about to perform a refreshoperation, the SNAP device relinquishes control by de-asserting theREQUEST and GRANT signals. Upon completion of the refresh cycle, theSNAP can once again arbitrate for control of the memory bus by assertinga REQUEST, and awaiting a GRANT that will be generated by the northbridge component's internal arbitration mechanisms. For conventionaloperation, the GRANT line is tied permanently to a signal stateindicating north bridge control (e.g., low in FIG. 8), and theREQUEST/REFRESH lines are unused so that north bridge component retainscontinuous control.

While there have been described above the principles of the presentinvention in conjunction with specific computing system architecturesand components, it is to be clearly understood that the foregoingdescription is made only by way of example and not as a limitation tothe scope of the invention. Particularly, it is recognized that theteachings of the foregoing disclosure will suggest other modificationsto those persons skilled in the relevant art. Such modifications mayinvolve other features which are already known per se and which may beused instead of or in addition to features already described herein.Although claims have been formulated in this application to particularcombinations of features, it should be understood that the scope of thedisclosure herein also includes any novel feature or any novelcombination of features disclosed either explicitly or implicitly or anygeneralization or modification thereof which would be apparent topersons skilled in the relevant art, whether or not such relates to thesame invention as presently claimed in any claim and whether or not itmitigates any or all of the same technical problems as confronted by thepresent invention. The applicants hereby reserve the right to formulatenew claims to such features and/or combinations of such features duringthe prosecution of the present application or of any further applicationderived therefrom.

Although the invention has been described and illustrated with a certaindegree of particularity, it is understood that the present disclosurehas been made only by way of example, and that numerous changes in thecombination and arrangement of parts can be resorted to by those skilledin the art without departing from the spirit and scope of the invention,as hereinafter claimed.

1. A computing system comprising: at least one microprocessor; a memorysubsystem coupled to the at least one microprocessor; a memorycontroller in a chipset of the computing system for issuing read andwrite commands to the memory subsystem and receiving data that resultsfrom the read and write commands coupled to manage memory transactionsbetween the memory subsystem and the at least one microprocessor; one ormore external devices including an independent memory controller forissuing read and write commands to the memory subsystem and receivingdata that results from the read and write commands coupled to the memorysubsystem so as to have access to the memory subsystem without goingthrough the memory controller; and at least one arbitration port coupledto the memory controller and configured to receive an externalarbitration signal from the one or more external devices, wherein theone or more external devices utilize the external arbitration signal toaccess the memory subsystem.
 2. The computing system of claim 1 whereinthe arbitration port is implemented in a north bridge component of asystem chipset.
 3. The computing system of claim 2 further comprising: aplurality of interface ports implemented by the north bridge component,each of the plurality of interface ports supporting memory transactionsfrom external systems; and an arbitration mechanism within the northbridge component for arbitrating amongst the plurality of interfaceports for access to the memory subsystem, wherein the at least onearbitration port couples to the arbitration mechanism.
 4. The computingsystem of claim 2 further comprising: a plurality of interface portsimplemented by the north bridge component, each of the plurality ofinterface ports supporting memory transactions from external systems; aninternal arbitration mechanism within the north bridge component forarbitrating amongst the plurality of interface ports for access to thememory subsystem; and an external arbitration mechanism coupled toprovide the arbitration signal over the arbitration port to the internalarbitration mechanism.
 5. The computing system of claim 1 wherein thearbitration port is implemented in a memory controller.
 6. The computingsystem of claim 1 wherein the memory controller is integrated with theat least one microprocessor and the arbitration port is implemented inthe memory controller of the microprocessor.
 7. The computing system ofclaim 1 wherein one or more external devices access the at least onearbitration port to conduct transactions with the memory subsystem.
 8. Asymmetric multiprocessor (SMP) computer system comprising: at least twomicroprocessors; a shared system memory; a memory controller coupled tothe shared system memory and the at least two microprocessors forissuing read and write commands to the shared system memory andreceiving data that results from the read and write commands wherein thememory controller is implemented in a north bridge component of a systemchipset; one or more external devices including an independent memorycontroller for issuing read and write commands to the shared systemmemory and receiving data that results from the read and write commandscoupled to the shared system memory such that a data path from theshared system memory to the at least one external device does not passthrough the memory controller implemented in the north bridge component;and a memory arbitration port within the memory controller andconfigured to receive an external arbitration signal from the one ormore external devices to control the data flow of the data path.
 9. TheSMP computer system of claim 8 wherein an arbitration mechanism includesresources for preventing access to specified memory locations by a firstof the at least two microprocessors when the specified memory locationsare in use by a second of the at least two microprocessors.
 10. The SMPcomputer system of claim 8 wherein an arbitration mechanism includesresources for reserving specified memory locations for exclusive accessby a subset of the at least two microprocessors.
 11. A computing systemcomprising: at least one microprocessor; a memory subsystem; an IOsubsystem; a memory/IO controller in a chipset of the computing systemcoupled to manage transactions between the memory subsystem and the I/Osubsystem and the at least one microprocessor; one or more externaldevices containing independent memory controllers to couple the externaldevices to the memory subsystem so as to have access to the memorysubsystem without utilizing the memory IO controller of the chipset,wherein one of the external devices includes a memory request arbiter;and at least one arbitration port coupled to the memory/IO controller ofthe chipset and configured to receive an external arbitration signalfrom the external device including the request arbiter, wherein the oneor more external devices utilize the external arbitration signal to gaindirect access to perform autonomous transactions to the memorysubsystem.
 12. The computing system of claim 11 wherein the arbitrationmechanism is implemented in a memory/IO component of a system chipset.13. The computing system of claim 12 further comprising: a plurality ofinterface ports implemented by the north bridge component, each of theplurality of interface ports supporting memory transactions fromexternal systems; and an arbitration mechanism within the north bridgecomponent for arbitrating amongst the plurality of interface ports foraccess to the memory subsystem, wherein the at least one arbitrationport couples to the arbitration mechanism.
 14. The computing system ofclaim 12 further comprising: a plurality of interface ports implementedby the north bridge component, each of the plurality of interface portssupporting memory transactions from external systems; an internalarbitration mechanism within the north bridge component for arbitratingamongst the plurality of interface ports for access to the memorysubsystem; and an external arbitration mechanism coupled to provide thearbitration signal over the arbitration port to the internal arbitrationmechanism.
 15. The computing system of claim 11 wherein the memorycontroller is integrated with the at least one microprocessor and therequest arbiter is implemented in the memory controller of themicroprocessor.
 16. A symmetric multiprocessor (SMP) computer systemcomprising: at least two microprocessors; a memory subsystem; amemory/IO controller coupled to the memory subsystem and the at leasttwo microprocessors wherein the memory/IO controller is implemented in asystem chipset; one or more external devices containing memorycontrollers coupled to the memory subsystem such that the externaldevices have an independent transaction path to and from the memory; amemory arbitration port within the memory/IO controller of the chipsetand configured to receive an external arbitration signal from the one ormore external devices; and a transaction arbiter in one of the externaldevices to provide the arbitration control signal to the memory/IOcontroller in the chipset.
 17. The SMP computer system of claim 16wherein an arbitration mechanism includes resources for preventingaccess to specified memory locations by a first of the at least twomicroprocessors when the specified memory locations are in use by asecond of the at least two microprocessors.
 18. The SMP computer systemof claim 16 wherein an arbitration mechanism includes resources forreserving specified memory locations for exclusive access by a subset ofthe at least two microprocessors.